A typical processing system with video/graphics display capability includes a central processing unit (CPU), a display controller coupled with the CPU by a system bus, a system memory also coupled to the system bus, a frame buffer coupled to the display controller by a local bus, peripheral circuitry (e.g., clock drivers and signal converters), display driver circuitry, and a display unit. The CPU generally provides overall system control and, in response to user commands and program instructions retrieved from the system memory, controls the contents of graphics images to be displayed on the display unit. The display controller, which may for example be a video graphics architecture (VGA) controller, generally interfaces the CPU and the display driver circuitry, exchanges graphics and/or video data with the frame buffer during data processing and display refresh operations, controls frame buffer memory operations, and performs additional processing on the subject graphics or video data, such as color expansion. The display driver circuitry converts digital data received from the display controller into the analog levels required by the display unit to generate graphics/video display images. The display unit may be any type of device which presents images to the user conveying the information represented by the graphics/video data being processed. The "display" may also be a printer or other document view/print appliance.
The frame buffer and system memory are typically constructed from read/write memory devices such as dynamic random access memories (DRAMs). These devices are typically arranged as rows and columns of cells, with a single bit storage cell disposed at each intersection of a row and a column. In most video and graphics applications, words of data (of 8, 16, 32 or more bits in length) are stored in adjacent cells in the array--namely in adjacent cells along the same row. Page mode accessing is then typically used to access one or more words from a given row during a single address cycle to improve processing speed. During a DRAM page mode access (either a read or a write), a row address is presented to the device address port and latched in with a row address strobe (RAS) to select a given row in the array. A column address is next presented to the address port and latched in with a column address strobe (CAS) to select a first column thereby allowing access to a first cell (bit) along the selected row. Column decode (static or dynamic) circuitry then increments from the received column address to generate a sequence of column addresses to adjacent columns, thereby allowing access to a "page" of cells (bits) along the selected row.
While the page mode allows for faster access, implementing it has substantial disadvantages. First, the RAS and CAS signals must be maintained low to latch the initial row and column addresses; CAS must be cycled for each page bit, the amount of time RAS and CAS are held low is limited (currently to approximately 10 .mu.sec maximum) due to the "dynamic" nature of the DRAM peripheral circuitry (e.g., on chip clocks). This limitation in turn limits the number of bits (cells) which may be accessed during a single page cycle. Further, the need to increment through the page on a single column by column basis increases cycle time per page. Finally, currently available DRAMs operating in the page mode do not allow random access of any desired specific bits along a given row and therefore typically a random access cycle may have been performed to access a selected bit.
Improved DRAMs with page mode access, such as the fast page mode and ultra fast page mode DRAMs, have been developed which provide for even faster access to pages of bits. These devices achieve the additional speed by replacing some of the clocked elements used in conventional page mode DRAM to transfer data from the columns to the data I/O pins with static devices. While this technique eliminates some of the gate delays in the data path, the use of static devices increases power consumption.
Thus, the need has arisen for an improved read/write memory with page mode access. Such a memory should allow for the fast access of long pages without consuming an excess of power. Further, such a memory should allow for the access of a selected bit or bits without the need to perform a full page cycle or random access. Finally, such a memory should be adapted for particular application in graphics and video data processing systems.